In semiconductor packages using a lead frame represented by a quad flat package (QFP), outer leads for connection with a printed circuit board are disposed on side surfaces of the semiconductor package.
Such a lead frame is allowed to obtain a semiconductor element mounting section, inner leads acting as sections for connection with semiconductor element electrodes, outer leads, and an outer frame section fixing them by forming predetermined photoresist patterns on both surfaces of a metal plate and etching the both surfaces of the metal plate. Further, these sections can be obtained by punching using a press in addition to the etching method.
In an assembly process of the semiconductor package, the semiconductor element is die-bonded onto the semiconductor element mounting section, and then the electrodes of the semiconductor element are electrically connected with the inner leads using, for instance, gold wires. Afterwards, the surroundings of the semiconductor element including the inner leads are encapsulated with a resin, and the outer frame section is cut off. If necessary, the outer leads are bent.
In this way, the outer leads disposed on the side surfaces are limited to a range from 200 to 300 pins in a package size of about 30 mm2 from the viewpoint of a processing ability of miniaturization.
In recent years, as the number of electrodes of the semiconductor element increases, a lead frame type semiconductor package having outer leads on side surfaces thereof cannot have a terminal number corresponding to the electrode number. Some external connection terminals of, for example, a ball grid array (BGA) type or a land grid array (LGA) type for connection with a printed circuit board are replaced by a semiconductor package disposed in an array shape on a bottom surface of a package substrate.
The substrates used for these packages are generally configured to drill holes through a glass epoxy substrate having copper bonded on both surfaces thereof, bring a wall of each hole into conduction by means of plating, and form terminals for connection with the electrodes of the semiconductor element on one of the surfaces and external connection terminals arranged in an array shape on the other surface.
However, the manufacturing of the substrates requires a complicated process as well as a high cost, and provides low reliability compared to the lead frame type package because the plating is used to connect interconnections within the substrate.
For this reason, a BGA type semiconductor package structure using a lead frame, in which a process of etching the lead frame from both surfaces is used, is disclosed (e.g., Patent Document 1).
In this structure, connection terminals for semiconductor element electrode are formed on one surface and external connection terminals are formed in an array form on the other surface by changing two photoresist patterns and etching the patterns at the same time or by etching one of the photoresist patterns, coating a pre-mold resin on the etched surface, and then etching the other photoresist pattern.    Patent Document 1: Japanese Patent No. 3642911